1. Field of Invention
This invention relates to improvements in methods and circuits for operating polyphase motors, such as a spindle motor of a mass data storage device, or the like, and more particularly to improvements in such driving methods and circuits that at least reduce the effects of current spikes that may occur in conjunction with a turn-on or commutation transition of driving currents in such motor.
2. Relevant Background
This invention relates primarily to improvements in circuitry for use in the operation of spindle motors of mass data storage devices, although it may be used in other motor applications, as well. Mass data storage devices include tape drives, as well as hard disk drives that have one or more spinning magnetic disks or platters onto which data is recorded for storage and subsequent retrieval. Mass data storage devices may also include optical disks in which the optical properties of a spinning disk are locally varied to provide a reflectivity gradient that can be detected by a laser transducer head, or the like. Hard disk drives may be used in many applications, including personal computers, set top boxes, video and television applications, audio applications, or some mix thereof. Optical disks may be used, for example, to contain data, music, or other information. Applications for hard disk drives are increasing in number, and are expected to further increase in the future.
Typically, mass data storage devices use polyphase, usually three-phase, DC motors to rotate the memory media. A typical polyphase motor has a xe2x80x9cYxe2x80x9d connected coil assembly driven by three respective MOS driving circuits Each driving circuit typically has a pull-up and a pull-down transistor connected in series between a supply rail and a reference potential, or ground. The pull-up transistors are generally referred to as xe2x80x9chigh-side driversxe2x80x9d (HSDs), and the pull-down transistors are generally referred to as xe2x80x9clow-side driversxe2x80x9d (LSDs). The node between the high and low side drivers of each driving circuit is connected to a respective end of one of the motor coils. The respective high and low side driver transistors are controlled by a sequencer or commutator circuit (not shown) in known manner to operate the circuit in successive states to direct a drive current through selected coils of the motor to spin it.
In the operation of such polyphase motors, pulse width modulation (PWM) techniques are often employed. PWM techniques are used to vary the duty cycle of the driving waveform so that a sensed average motor current matches a current command signal representing the desired motor speed. In normal PWM operation of the bridge FETs, since the PWM frequency is sufficiently high, the bulk capacitance of the power supply is generally able to contribute part of the current needed by the spindle motor current control loop.
However, when a low side driver transistor is commutated to draw current, the current through the transistor must rise from zero to the peak current. During this time, PWM operation is not employed, and the current pulse can become very wide relative to the current pulses seen during normal PWM chopping of the driver transistors. This reduced frequency may have the effect of totally draining the bulk capacitance of the power supply. When the bulk capacitance is drained, it no longer is able to contribute current to the motor. Thus, during this time, all current comes from the power supply. The result is that shortly after the commutation point of the low-side driver transistors, the current seen at the power supply has a current spike that is higher than the current seen during normal PWM operation.
The nature of this current spike is shown in FIG. 1, to which reference is now made. As shown, the commutation current 5 is illustrated as a function of time, in comparison to the power supply current 7. This can be seen, after the initial ramp up of the commutation current in graph 5, the power supply current in graph 7 similarly begins to ramp up. However, as shown, a spike 9 occurs, which is undesirable.
What is needed, therefore, Is a method and circuit for substantially reducing or eliminating the current spike that is seen by the power supply after a commutation of the driving current of a polyphase motor.
In light of the above, therefore, it is an advantage of the invention that the current spike that may be seen by the power supply after a turn-on or commutation of the driving current of a polyphase motor can be reduced or eliminated.
It is another advantage of the invention that the solution advanced herein is an adaptive as to the number of extra PWM cycles required to reach the peak current.
It is another advantage of the invention that the technique described herein minimizes the number of cycles through the use of a timeout timer used prior to actually adding the extra PWM cycles.
It is yet another advantage of the invention that the added PWM cycles need not have a 50 percent duty cycle, but can be selected according to the application.
Thus, according to a broad aspect of the invention, a method is presented for reducing a current spike created after a commutation of a driving current of a polyphase motor. The method includes timing a first delay after the commutation of the driving current. Thereafter, the driving current pulse width modulated, and a determination is made when the driving current has reached a predetermined value. Finally, the pulse width modulating is discontinued. In a preferred embodiment, normal PWM modulation of the dc voltage is resumed after the current induced in the one of the coils has reached a peak value. According to another broad aspect of the Invention, a method is presented for operating a polyphase motor. The method includes timing a first delay after a commutation of a driving current of the motor, and thereafter, pulse width modulating the driving current. A determination is made determining when the driving current has reached a predetermined value, and thereafter, the pulse width modulating is discontinued. Finally, a normal pulse width modulation is applied to the driving current.
According to yet another broad aspect of the invention, a circuit for driving a polyphase motor having a plurality of coils that are driven by a commutated dc voltage from a power supply. The circuit includes a circuit for detecting a commutation of the dc voltage and a circuit for reducing a current spike in the dc voltage from the power supply a time before a current induced in one of the coils reaches a peak value. In a preferred embodiment, the circuit for reducing a current spike in the dc voltage from the power supply is a circuit for PWM modulating the dc voltage during at least a portion of a time before a current induced in one of the coils reaches a peak value. In a preferred embodiment, the at least a portion of a time begins a delayed time after the commutation and ends when the current reaches the peak value. Also, in a preferred embodiment, a circuit is provided for additionally PWM modulating the dc voltage after the current induced in the one of the coils has reached a peak value.
According to yet another broad aspect of the invention, a circuit is provide for driving a polyphase motor having a plurality of coils that are driven by a commutated dc voltage from a power supply. The circuit includes a circuit for detecting a commutation of the dc voltage and a circuit for PWM modulating the dc voltage during at least a portion of a time before a current induced in one of the coils reaches a peak value. In a preferred embodiment, the at least a portion of a time begins a delayed time after the commutation and ends when the current reaches the peak value. In a preferred embodiment, a circuit is also provided for additionally PWM modulating the dc voltage after the current induced in the one of the coils has reached a peak value.
In still yet another broad aspect of the invention, a circuit is provided for driving a polyphase motor having a plurality of coils that are driven by a commutated dc signal from a power supply. The circuit includes a circuit for detecting a commutation of the dc voltage and a circuit for timing a delay time after the commutation. A circuit is provided for PWM modulating the dc voltage after the delay time, and a circuit is provided for discontinuing the PWM modulating after a current induced in one of the coils has reached a peak value. In a preferred embodiment, the at least a portion of a time begins a delayed time after the commutation and ends when the current reaches the peak value. In a preferred embodiment, a circuit is provided for additionally PWM modulating the dc voltage after the current induced in the one of the coils has reached a peak value.
According to another broad aspect of the invention, a circuit is provided for driving a polyphase motor having a plurality of coils that are driven by a commutated dc signal from a dc power supply. The circuit includes a gate having first and second inputs and having an output connected to deliver drive signals for application to one of the coils. A source of clock pulses is connected to the first input of the gate, and a detection circuit detects a commutation of the dc voltage.
A counter circuit counts to a start time after the detection circuit detects the commutation and before a current induced in the one of the coils has reached a peak value to deliver a start signal to the second input of the gate, wherein the output of the gate includes PWM signals after the start time. A circuit is also provided for discontinuing the PWM signals after the current induced in the one of the coils has reached the peak value. In a preferred embodiment, a circuit is also provided for additionally PWM modulating the dc voltage after the current induced in the one of the coils has reached a peak value.
According to yet still another broad aspect of the invention, a mass data storage device is provided. The mass data storage device includes a polyphase motor having a plurality of coils and a dc power supply to supply a dc voltage. A commutator circuit commutates the dc voltage for application to selected ones of the coils, and a plurality of gates are provided, each having first and second inputs and having an output connected to deliver drive signals for application to a respective one of the coils. A detection circuit detects a commutation of the dc voltage by the commutator circuit. A source of clock pulses Is connected to the first inputs of the gates, and a counter circuit counts to a start time after the detection circuit detects the commutation and before a current induced in the one of the coils has reached a peak value to deliver a start signal to the second input of the gate. The output of the gate therefore includes PWM signals after the start time. A circuit discontinues the PWM signals after the current induced in the one of the coils has reached the peak value. In a preferred embodiment, a circuit is provided for additionally PWM modulating the dc voltage after the current induced in the one of the coils has reached a peak value.